发明名称 |
Reconfigurable processing system including synchronized postprocessing |
摘要 |
Source code to be processed is analyzed and configuration data in implementing in accordance with each of plural implementation systems is created and is stored in a local memory of a DRP incorporating system. When execution of target processing is started, the implementation system determination processing calculates estimated processing time when the configuration of each of the implementation systems is adopted and determines the optimum one of the implementation systems based on a combination of the estimated processing time and the circuit scale of the configuration. |
申请公布号 |
US8719550(B2) |
申请公布日期 |
2014.05.06 |
申请号 |
US20100869200 |
申请日期 |
2010.08.26 |
申请人 |
NAITO TAKAO;YAMADA KAZUO;FUJI XEROX CO., LTD. |
发明人 |
NAITO TAKAO;YAMADA KAZUO |
分类号 |
G06F15/00;G06F15/76 |
主分类号 |
G06F15/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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