| 摘要 |
This disclosure describes a low-density parity-check (LDPC) decoder that is configured to decode a codeword using an iterative process. The decoder includes a memory to store the codeword and a first syndrome memory configured to store a syndrome result determined in a previous iteration. The decoder further includes circuitry to flip bits of the codeword based on the syndrome result and one or more parity-check equations, and a second syndrome memory configured to update a current syndrome result during a current iteration based on the bits of the codeword that are flipped by the circuitry. |
