发明名称 |
Memory apparatus and testing method thereof |
摘要 |
A memory apparatus and a related testing method are provided in the present invention. The memory apparatus includes a memory and a testing module. The testing module includes an error recording unit for recording corresponding addresses of bit errors occurred in the memory. The testing module determines whether the memory has multi-bit error according to the addresses recorded in the error recording unit. The memory is an ECC memory.
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申请公布号 |
US8572444(B2) |
申请公布日期 |
2013.10.29 |
申请号 |
US20100722538 |
申请日期 |
2010.03.12 |
申请人 |
LEE JIH-NUNG;KUO SHUO-FEN;WU CHI-FENG;REALTEK SEMICONDUCTOR CORP. |
发明人 |
LEE JIH-NUNG;KUO SHUO-FEN;WU CHI-FENG |
分类号 |
G11C29/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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