SYSTEM AND METHOD OF CLOCKING LOW SAMPLE RATE ANALOG TO DIGITAL CONVERTERS WHILE MINIMIZING LINEARITY ERRORS

摘要

A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.