发明名称 BINARY ADDER
摘要 A binary adder comprises first and second computing units, wherein first and second inputs of the binary adder are connected to corresponding inputs of first computing unit which output is connected to first input of second computing unit which second input is connected to third input of the binary adder, and output of second computing unit is connected to first output of the binary adder. Analog adder and two inverters are additionally introduced.
申请公布号 UA83134(U) 申请公布日期 2013.08.27
申请号 UA20130003253U 申请日期 2013.03.18
申请人 V. HLUSHKOV INSTITUTE OF CYBERNETICS OF THE NAS OF UKRAINE 发明人 PALAHIN OLEKSANDR VASYLIIOVYCH;BOIUN VITALII PETROVYCH;KLIMOVSKA ALLA IVANIVNA;BILYK VIKTOR KYRYLOVYCH
分类号 G06F7/502 主分类号 G06F7/502
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