发明名称 TRACKING CAPACITIVE LOADS
摘要 A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.
申请公布号 US2013215693(A1) 申请公布日期 2013.08.22
申请号 US201213399877 申请日期 2012.02.17
申请人 TAO DEREK C.;KIM YOUNG SEOG;HSU KUOYUAN (PETER);WANG BING;LUM ANNIE-LI-KEOW;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 TAO DEREK C.;KIM YOUNG SEOG;HSU KUOYUAN (PETER);WANG BING;LUM ANNIE-LI-KEOW
分类号 G11C7/00 主分类号 G11C7/00
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