发明名称 METHOD TO OPTIMIZE AND REDUCE INTEGRATED CIRCUIT, PACKAGE DESIGN, AND VERIFICATION CYCLE TIME
摘要 A method for fabricating an integrated circuit (IC) product and IC product formed thereby. The method includes designing an IC package having a plurality of IC connection sets, each configured to be connected to a corresponding IC selected from among a plurality of ICs, each having different functionality. Various IC products can be produced depending upon which selected IC is connected to its corresponding connection set, and the IC package can be cut during design to exclude IC connection sets corresponding to ICs that are not selected. By testing the complete IC package, a portion of the complete IC package can be fabricated, cut from the complete IC package, with significantly reduced design and testing requirements.
申请公布号 KR20130070643(A) 申请公布日期 2013.06.27
申请号 KR20137010193 申请日期 2011.09.22
申请人 QUALCOMM INCORPORATED 发明人 LANE RYAN D.;ZANG RUEY KAE
分类号 G06F17/50 主分类号 G06F17/50
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