发明名称 |
Simplified architecture for defuzzification integrated circuit (IC) processor including circuits for estimating effective areas without overlapping errors |
摘要 |
A digital defuzzification processor implemented as integrated circuits (ICs). The defuzzification IC processor includes an input port for receiving a plurality of input values and a corresponding set of specific weight and an effective area for each of the input values. The defuzzification IC processor further includes a multiplier for multiplying each of the input values to the corresponding specific weight for generating a plurality of partial-input-weighted-specific-weight, the multiplier further multiplying the each of the input values to the corresponding effective area for generating a plurality of partial-input-weighted-effective-area. The defuzzification IC processor further includes an accumulator for adding each of the plurality of partial input-weighted-specific-weight for generating a summed-input-weighted specific-weight, the accumulator further adding each of the plurality of partial-input-weighted-effective-area for generating a summed-input weighted-effective-area. The defuzzification IC processor further includes a divider for dividing the summed-input-weighted-specific-weight by the summed-input-weighted-effective-area for generating a crisp output.
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申请公布号 |
US5852708(A) |
申请公布日期 |
1998.12.22 |
申请号 |
US19960676909 |
申请日期 |
1996.07.08 |
申请人 |
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE |
发明人 |
SHYU, JYUO-MIN;LU, YAO-CHOU;DENG, HSI-CHOU;CHENG, HSU-HUANG |
分类号 |
G06F9/44;G06N7/02;G06N7/04;(IPC1-7):G06G7/00 |
主分类号 |
G06F9/44 |
代理机构 |
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主权项 |
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地址 |
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