发明名称
摘要 <p>A semiconductor memory device conducts a burst read operation that avoids interrupt loading on a system. The memory device includes a memory cell array, a sense amplifier, a latch circuit and a burst mode control unit. The sense amplifier is configured to sequentially sense and amplifies data stored in the memory cell array. The latch circuit is configured for latching sensed data of the sense amplifier group and outputting the sensed data in response to a DUMP signal. The burst mode control unit is configured for detecting the length of invalid data included in the sensed data from a burst start address and controlling a point in time of DUMP signal generation according to the detection result to sequentially output only valid data among the sensed data.</p>
申请公布号 JP5101123(B2) 申请公布日期 2012.12.19
申请号 JP20070024494 申请日期 2007.02.02
申请人 发明人
分类号 G11C16/02;G11C16/04;G11C16/06 主分类号 G11C16/02
代理机构 代理人
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