发明名称 |
Method and apparatus for simultaneous switching noise optimization |
摘要 |
Methods and apparatus for reducing simultaneous switching noise (SSN) in an integrated circuit (IC) designed with a computer aided design (CAD) tool are presented. In one method, value assignments for parameters of the IC are received by the CAD tool. The value assignments are entered as a range of value assignments or as a list of possible value assignments. Further, the method includes an operation for determining the minimum and the maximum path delays for each Input/Output (I/O) pin in an I/O block such that the received value assignments are satisfied. The actual switching times of the I/O pins are spread out in time to decrease SSN in the I/O pins. The switching times are spread out so that the switching times fall between the minimum and the maximum path delay for the corresponding I/O pin. Additionally, other method operations are included for routing paths to the I/O pins to meet the actual switching times and for creating a design for the IC that meets the actual switching times. |
申请公布号 |
US8296704(B1) |
申请公布日期 |
2012.10.23 |
申请号 |
US20100833797 |
申请日期 |
2010.07.09 |
申请人 |
KIPPER MICHAEL HOWARD;FENDER JOSHUA DAVID;AZIZI NAVID;GOLDMAN DAVID SAMUEL;ALTERA CORPORATION |
发明人 |
KIPPER MICHAEL HOWARD;FENDER JOSHUA DAVID;AZIZI NAVID;GOLDMAN DAVID SAMUEL |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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