| 摘要 |
<P>PROBLEM TO BE SOLVED: To perform acceleration while suppressing increase of an area of a cache memory. <P>SOLUTION: A cache memory 2 comprises a plurality of ways including a plurality of cache lines having a tag memory 103, a first dirty bit memory 106, an effective bit memory 107, and a data memory 105. Also, the cache memory 2 is provided with a line index memory 101 for specifying the cache line. Also, the cache memory 2 comprises a DBLB system 201 including a plurality of lines having a row memory 202 for storing first bit data specifying the way and second bit data specifying a line index, a second dirty bit memory 203 for storing a second dirty bit of a bit unit corresponding to write of a byte unit to the data memory, and a FIFO memory 204 for storing FIFO information defining the order of registration. <P>COPYRIGHT: (C)2013,JPO&INPIT |
