发明名称 I2C-bus interface with parallel operational mode
摘要 An electronic circuit has an interface for an I2C-bus. The interface comprises a first node for a clock line of the I2C-bus; a second node for a data line of the I2C-bus; and an I2C-bus controller for controlling an operation of the interface under combined control of the clock line and the data line. The circuit has a plurality of further nodes for connecting to a plurality of further data lines. The controller has an operational mode for control of receiving from the further nodes, or for control of supplying to the further nodes, a plurality of data bits in parallel under combined control of the clock line and the data line.
申请公布号 US8266360(B2) 申请公布日期 2012.09.11
申请号 US20080672948 申请日期 2008.08.13
申请人 AGRAWAL SANDEEP;NXP B.V. 发明人 AGRAWAL SANDEEP
分类号 G06F13/14 主分类号 G06F13/14
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