发明名称 |
Latch Circuits with Synchronous Data Loading and Self-Timed Asynchronous Data Capture |
摘要 |
A latch integrated circuit has synchronous data loading and self-timed asynchronous data capture characteristics. The integrated circuit may include a latch, a pulse generator and a comparator. The latch can be responsive to a data signal and a write enable signal. The pulse generator may be configured to generate the write enable signal as a pulse. This pulse may have a leading edge synchronized with a first edge of a clock signal and a self-timed trailing edge synchronized with an edge of a comparison signal. The comparator may be configured to generate the comparison signal in response to comparing logic levels of at least two nodes within the integrated circuit. |
申请公布号 |
US2012112813(A1) |
申请公布日期 |
2012.05.10 |
申请号 |
US20100940078 |
申请日期 |
2010.11.05 |
申请人 |
HOFF DAVID PAUL;HAMDAN FADI ADEL;QUALCOMM INCORPORATED |
发明人 |
HOFF DAVID PAUL;HAMDAN FADI ADEL |
分类号 |
H03K3/00 |
主分类号 |
H03K3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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