发明名称 |
INJECTION-LOCKED FREQUENCY DIVIDER AND PLL CIRCUIT |
摘要 |
Disclosed are a PLL circuit and an injection-locked frequency divider that can lessen the effect of parasitic capacitance and wherein the operating frequency is broadband. The injection-locked frequency divider (100) is provided with: a first amplification circuit (141) configured from an N-channel MOS transistor (111) and a P-channel MOS transistor (112); a ring oscillator (140) wherein a second amplification circuit (142) and a third amplification circuit (143) having a similar configuration have a ring-shaped three-stage cascade connection; an N-channel MOS transistor (150) wherein the source of the N-channel MOS transistor (111, 121, 131) of each stage is connected to the drain thereof; and a differential signal injection circuit (160) that injects an injection signal (I1) to the gate of the P-channel MOS transistor (112, 122, 132) of each stage and that injects a reversed-phase signal of the injection signal (I1) as a differential signal to the gate of the N-channel MOS transistor (150). |
申请公布号 |
WO2011089918(A1) |
申请公布日期 |
2011.07.28 |
申请号 |
WO2011JP00317 |
申请日期 |
2011.01.21 |
申请人 |
PANASONIC CORPORATION;SHIMA, TAKAHIRO;SATO, JUNJI;KOBAYASHI, MASASHI |
发明人 |
SHIMA, TAKAHIRO;SATO, JUNJI;KOBAYASHI, MASASHI |
分类号 |
H03K3/354;H03K3/03;H03K27/00;H03L7/08;H03L7/10 |
主分类号 |
H03K3/354 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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