| 摘要 |
878,333. Electronic counting-apparatus. VAN DER HEEM N.V. Jan. 7, 1960 [Feb. 7, 1959], No. 651/60. Class 106 (1). A decimal counter comprises four cascaded bi-stable circuits B1-B4, the second and fourth circuits being so coupled that the second B2 is blocked in its quiescent state as long as the fourth B4 is in its quiescent state, and the fourth circuit B4 being triggered from its quiescent to its active state by the output from the first circuit B1. The second input pulse at 1 restores B1 to normal, B1 producing an output which is ineffective at B2 because B4 is quiescent. However, this output pulse renders B4 active so that for subsequent input pulses the stages B1-B3 act as a normal binary cascade counter. The tenth input pulse turns all stages off and produces an output pulse at 2. Circuit details are shown in Fig. 3 (not shown) with a feedback from the collector of a transistor in stage B4 through a resistor 3 maintaining a transistor of stage B2 conducting as long as the transistor in stage B4 is non-conducting. |
