发明名称 |
Input stage for mixed-voltage-tolerant buffer with reduced leakage |
摘要 |
A mixed-voltage buffer circuit coupled between a first circuit operative at a first power supply voltage and a second circuit operative at a second power supply voltage. The buffer circuit is connectable to the second power supply voltage and a third power supply voltage and includes an input circuit coupled to the first circuit through a first node and to the second circuit through a second node. The input circuit includes a first part coupled to the first node and an inverter coupled to the second node. The first part provides a signal having a voltage level approximately equal to the third power supply voltage to the inverter in response to a first signal on the first node, and provides a signal having a voltage level approximately equal to the second power supply voltage to the inverter in response to a second signal on the first node.
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申请公布号 |
US7969190(B2) |
申请公布日期 |
2011.06.28 |
申请号 |
US20090405103 |
申请日期 |
2009.03.16 |
申请人 |
CHUANG CHE-HAO;KER MING-DOU |
发明人 |
CHUANG CHE-HAO;KER MING-DOU |
分类号 |
H03K19/0175;H03K19/00;H03K19/003;H03K19/0185 |
主分类号 |
H03K19/0175 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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