发明名称 Constraint based retiming of synchronous circuits
摘要 In one embodiment of the invention, a method of retiming a circuit is disclosed. The method includes computing an upper bound and a lower bound for a clock period of a clock signal to clock a circuit in response to a netlist of the circuit; selecting a potential clock period for the clock signal to clock registers of the circuit in response to the computed upper bound and the computed lower bound for the clock period; computing an upper bound and a lower bound of a retiming value for each node of the circuit to determine if a retiming of the circuit is achievable with the potential clock period; and computing the retiming value for each node of the circuit to minimize circuit area in response to the computed upper bound and the computed lower bound of the retiming value for each node.
申请公布号 US7945880(B1) 申请公布日期 2011.05.17
申请号 US20070755425 申请日期 2007.05.30
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 ALBRECHT CHRISTOPH;RICHTER SASCHA
分类号 G06F17/50;G06F9/45 主分类号 G06F17/50
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