| 摘要 |
A logic circuit for computing first and second modal interval (MI) result values is disclosed. The values are of at least first and second different MI functions responsive to respectively, first and second values of a selector signal. The computing is based on at least one MI operand value encoded in an operand signal. Each MI value comprises first and second multi-bit set theoretical numbers (STN) and the STNs define first and second end points of a range of real numbers. The logic circuit further encodes one of the universal and existential quantification values. The logic circuit includes at least first and second arithmetic functional units (AFUs) each connected to receive the operand signal. The AFUs perform an arithmetic operation using as the arguments therefor, each MI operand value encoded in the operand signal, and respectively provide the first and second MI result values in first and second result signals. The logic circuit also includes a multiplexer having a selector input receiving the selector signal having a multibit output port for providing an output signal encoding a MI result value, and having at least first and second multi-bit input ports. The first and second input ports are connected to receive respectively the first and second result signals provided as the operand signals by the first and second AFUs, and each input port is associated with a single selector signal value. The multiplexer supplies, encoded in an output signal provided by the output port, the MI result value provided at the input port thereof associated with the current selector signal value. The logic circuit also includes a result register for storing each MI result value, connected to receive the values respectively provided by the multiplexer output port. |
