| 摘要 |
PURPOSE: A delay locked loop circuit is provided to easily output the data synchronized with the external clock by improving the jitter property of a clock which is delay locked of a delay locked loop circuit. CONSTITUTION: A clock divider(13) divides and outputs the external clock. A delay model(22) models the transmission path of the external clock. A phase comparator(19) compares the output of the clock divider and the output of the delay model. A shift controller(18) controls the delay value of the delay line according to the output of the phase comparator. |
