RECONFIGURABLE LOGIC CIRCUIT, VERIFICATION METHOD AND VERIFICATION PROGRAM

摘要

<P>PROBLEM TO BE SOLVED: To suppress an increase in scale of a verification circuit mounted on a reconfigurable logic circuit when the number of assertions in assertion-based verification increases. Ž<P>SOLUTION: The reconfigurable logic circuit includes a designed circuit and a verification circuit for verifying the designed circuit. The verification circuit is shared in verifications based on a plurality of assertions included in assertion-based verification. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž