发明名称 ARITHMETIC UNIT, DECODER, MEMORY CONTROL METHOD, AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To reduce a storage area of a register group etc. for use in arithmetic processing. SOLUTION: An arithmetic unit includes: a register group 40 to be a memory where a plurality of data before subjected to arithmetic processing are stored in a plurality of prescribed areas respectively; and a control means for storing arithmetically processed data obtained by performing arithmetic operation of data before subjected to arithmetic processing read from the register group 40 in the plurality of prescribed areas of the register group 40 respectively. A decoder includes: a memory for storing a plurality of data showing states over N (N is an integer equal to or larger than 0) time points in viterbi decoding processing in a plurality of prescribed areas respectively; and a control means for respectively storing a plurality of data showing states over N+1 time points or N-1 time points to which prescribed arithmetic processing is applied to the plurality of data showing the states over the N time points when the data have been read from the memory. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010135918(A) 申请公布日期 2010.06.17
申请号 JP20080307680 申请日期 2008.12.02
申请人 NEC CORP;NTT DOCOMO INC 发明人 SHIMIZU MASAICHI
分类号 H03M13/41;H03M13/23 主分类号 H03M13/41
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