发明名称 DLL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
摘要 <P>PROBLEM TO BE SOLVED: To provide a DLL circuit capable of preventing the occurrence of malfunction due to aliasing. Ž<P>SOLUTION: The DLL circuit includes: a delay line 110 for generating an internal clock signal LCLK by delaying an external clock signal CLK; a counter circuit 130 for setting a delay amount of the delay line 110; a phase detection circuit 140 for generating a phase determination signal PD0 based on a phase of the external clock signal CLK; and an antialiasing circuit 200 for prohibiting the counter circuit 130 from updating a count value based on the phase determination signal PD in response to a state that a jitter component included in the external clock signal CLK is predetermined frequency and more. Consequently, a problem that the internal clock signal LCLK is continuously controlled to a wrong direction due to malfunction of aliasing does not occur. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010124020(A) 申请公布日期 2010.06.03
申请号 JP20080292940 申请日期 2008.11.17
申请人 ELPIDA MEMORY INC 发明人 KOBAYASHI KATSUTARO;KITAGAWA KATSUHIRO
分类号 H03L7/06;G11C11/407;G11C11/4076;H03L7/081 主分类号 H03L7/06
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