发明名称 SET ASIDE MECHANISM FOR INTERRUPTION POSTTRANSACTION
摘要 <P>PROBLEM TO BE SOLVED: To provide a method and device for eliminating delay of transaction because there are possibilities that it takes many hours for a processor from the time when it accepts interruption to the time when it returns a notice of completion indicating the acceptance and the transaction after that is delayed. Ž<P>SOLUTION: The method includes a step of receiving input posttransaction in a processor complex from peripheral devices and a step of determining whether transaction is interruption transaction, routing the transaction into a first queue if the transaction is the interruption transaction, and routing the transaction into a second queue if the transaction is not the interruption transaction. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010092474(A) 申请公布日期 2010.04.22
申请号 JP20090226716 申请日期 2009.09.30
申请人 INTEL CORP 发明人 WHITE BRYAN R;MORAN DOUGLAS
分类号 G06F9/48 主分类号 G06F9/48
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