| 摘要 |
A digital processing system, in which a single interrupt to a processor is used in transferring multiple messages in the form of corresponding packets. In an embodiment, a processor continues to write messages to a transmit first-in-first-out (FIFO) along with a length of the message in a header of a packet. A direct memory access (DMA) controller compares the length indicated in the header with the unread data in the transmit FIFO to determine whether a complete message is stored in the transmit FIFO. DMA controller starts transmission of only complete messages thereafter. A single interrupt is generated when no complete message is determined to be present in the transmit FIFO. Similar features may be used to reduce interrupts to the processors, when transmitting data to the processor.
|
