发明名称 TIMING CONSTRAINT MERGING IN HIERARCHICAL SOC DESIGNS
摘要 A method for propagating timing constraints from lower level design blocks to higher level design blocks includes o the steps of designing a circuit containing a plurality of design blocks. Each of the plurality of design blocks has a set of timing constraints associated therewith. A composite set of timing constraints is created for the circuit from each of the set of timing constraints associated with each of the plurality of design blocks, according to an established propagation rule set.
申请公布号 US2009271750(A1) 申请公布日期 2009.10.29
申请号 US20060095164 申请日期 2006.11.30
申请人 NXP B.V. 发明人 RICHARDSON JUDITH;PUTTASWAMY NIRANJAN A.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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