| 摘要 |
Disclosed is a column select signal adjusting circuit capable of reducing interference between bit lines and data lines and a semiconductor memory device having the same. The column select signal voltage adjusting circuit includes a driving voltage generating unit for producing a driving voltage when the write signal is activated, wherein a voltage level of the driving voltage produced when the write signal is activated is higher than a voltage level of the driving voltage produced when the write signal is inactivated, and a column select signal driving unit for outputting a column select signal by driving a decoding signal to the voltage level of the driving voltage.
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