发明名称 DEBUGGING DEVICE AND METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a debugging device and method, using a hardware emulator capable of always making an instruction execution interval between a verification target circuit and a duplication circuit a prescribed number of instructions. <P>SOLUTION: The debugging device includes: the hardware emulator 1; a software debugger 2 for controlling the hardware emulator 1; and a hardware debugger 3 for analyzing output of the hardware emulator 1. The hardware emulator 1 includes: a verification target circuit part 11; and a duplication circuit part 12 for duplicating the verification target circuit part 11. In the verification target circuit part 11, a start and a stop of operation is controlled by a debug control part 13. The duplication circuit part 12 starts operation by a prescribed number of delay instructions behind as compared to the verification target circuit part 11, based on the control of an execution start delay part 14. A program counter control part 15 controls update of respective program counters PC1, PC2 such that the instruction execution interval between the verification target circuit part 11 and the duplication circuit part 12 maintains the prescribed number of the delay instructions. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009193165(A) 申请公布日期 2009.08.27
申请号 JP20080030962 申请日期 2008.02.12
申请人 TOSHIBA CORP 发明人 AKIBA TAKASHI;MIURA TAKASHI
分类号 G06F11/22;G06F11/28;G06F17/50 主分类号 G06F11/22
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