发明名称 Logic circuit apparatus for selectively assigning a plurality of circuit data to a plurality of programmable logic circuits for minimizing total power while maintaining necessary processing performance
摘要 A logic circuit apparatus includes a plurality of programmable logic circuits, a circuit data memory, a control unit. The plurality of programmable logic circuits are each configured to have a changeable circuit component based on circuit data. Each programmable logic circuit has a different processing performance. The circuit data memory is used to store a plurality of circuit data and performance requirements for the circuit data. The control unit is configured to selectively assign the plurality of circuit data to the plurality of programmable logic circuits so that a total power of all programmable logic circuits minimizes on condition that the performance requirement of the circuit data assigned to each programmable logic circuit is within the processing performance of each programmable logic circuit.
申请公布号 US7533282(B2) 申请公布日期 2009.05.12
申请号 US20070949072 申请日期 2007.12.03
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 OHNEDA TAKU;KANNO SHINICHI;TARUI MASAYA;MIYAMOTO YUKIMASA;OGAWA RIKU
分类号 G06F1/00;G06F1/32;G06F1/08;G06F1/30;H03K19/00;H03K19/173 主分类号 G06F1/00
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