发明名称 |
Shift-add based parallel multiplication |
摘要 |
A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors, and the second memory holds a second value that is representative of multiple multiplicands that are other of the factors. A multiplier bit-count is determined of the significant bits in the multiplier. And a +* operation is performed with the first value and said second value a quantity of times equaling the multiplier bit-count.
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申请公布号 |
US2009083360(A1) |
申请公布日期 |
2009.03.26 |
申请号 |
US20080148515 |
申请日期 |
2008.04.18 |
申请人 |
ELLIOT GIBSON DANA;MOORE CHARLES H |
发明人 |
ELLIOT GIBSON DANA;MOORE CHARLES H. |
分类号 |
G06F7/523 |
主分类号 |
G06F7/523 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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