发明名称 Memory circuit having a crosstalk-glitch suppressor circuit and a control device for controlling an amount of suppression performed by the crosstalk-glitch suppressor circuit
摘要 The memory circuit comprises: a single or a plurality of reading-out port(s); a single or a plurality of writing port(s); a crosstalk-glitch suppressor circuit for suppressing crosstalk glitch between internal signal lines of each of the ports; and a control device for controlling capacity of the crosstalk-glitch suppressor circuit.
申请公布号 US7509607(B2) 申请公布日期 2009.03.24
申请号 US20050304775 申请日期 2005.12.16
申请人 PANASONIC CORPORATION 发明人 IKEDA YUUICHIROU
分类号 G06F9/45;G11C7/02;G11C8/00 主分类号 G06F9/45
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