TEST DEVICE AND TEST METHOD

摘要

There is provided a test apparatus that decides the good or bad of an electronic device adopting source synchronous clocking with high precision. A first variable delay circuit 210 in the test apparatus according to the present invention delays a data signal output from a device under test 100 by a designated time to output the delayed signal as a delay data signal. A second variable delay circuit 220 delays a clock signal showing a timing at which the data signal should be acquired, which is output from the device under test 100, by a designated time in order to output the delayed signal as a first delay clock signal. Delay amounts of these variable delay circuits are set by a first delay adjusting section 300. A third variable delay circuit 270 delays a clock signal output from the device under test 100 by a designated time to output the delayed signal as a second delay clock signal. A fourth variable delay circuit 285 delays a reference clock by a designated delay amount to supply the delayed clock to a first selecting section 280.