发明名称 DIFFERENTIAL OUTPUT CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a differential output circuit capable of reducing influence of noise due to charge injection with simple circuit constitution. SOLUTION: First to fourth transistors T1 to T4 are connected between first and second potentials VDD and VSS, differential clock signals are inputted to a first common gate of the transistors T1 and T3 and a second common gate of the transistors T2 and T4, and differential clock signals can be outputted from a first common drain of the transistors T1 and T3 and a second common drain of the transistors T2 and T4. First to fourth dummy transistors C1 to C4 are provided corresponding to the first to fourth transistors T1 to T4, clock signals which are opposite in phase to the clock signals supplied to the respective corresponding transistors are inputted to gates, and the dummy transistors turn on when the corresponding transistors turn off to cancel charge injection. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006115050(A) 申请公布日期 2006.04.27
申请号 JP20040298452 申请日期 2004.10.13
申请人 SEIKO EPSON CORP 发明人 YOKOYAMA HIDETOSHI
分类号 H03K17/16;H03K17/687;H03K19/0175 主分类号 H03K17/16
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