发明名称 OUT OF ORDER DRAM SEQUENCER
摘要 PROBLEM TO BE SOLVED: To provide a configuration and operation method of a memory controller, for control of memory access processing for increasing an effective bandwidth of a memory. SOLUTION: Memory access requests are successively received in an input queue of a memory controller. A sequence matrix is rearranged after reception of requests into the input queue, and conflicts or potential delays between sequential requests are identified by a conflict detector. The conflict detector re-orders the memory core access requests to optimize the flow of data to and from a data bus. For example, if a bank busy condition or other delay is recognized by the conflict detector in the sequentially received memory requests, the memory controller rearranges the order in which the pending memory requests will be executed to eliminate the conflict or delay, if possible, or otherwise to minimize the delay. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008204487(A) 申请公布日期 2008.09.04
申请号 JP20080140086 申请日期 2008.05.28
申请人 MICRON TECHNOLOGY INC 发明人 JEDDELOH JOSEPH M
分类号 G06F12/00;G06F;G06F12/06;G06F13/16 主分类号 G06F12/00
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