| 摘要 |
A receiver circuit ( 200 ) is provided, comprising: an agile clock ( 250 ) configured to generate an agile clock signal having a controllable agile clock phase based on agile clock control signals; a code processor ( 260 ) configured to receive an incoming signal and the agile clock signal, and to generate an on-time signal ( 110 ) and an error signal ( 120 ) corresponding to the incoming signal; a coarse acquisition circuit ( 270, 310 ) configured to identify a coarse acquisition phase based on a total power of the on-time signal and plus a total power of the error signal; a fine acquisition circuit ( 270, 320 ) configured to identify a fine acquisition phase based on the coarse acquisition phase and a magnitude of the on-time signal; and an acquisition controller ( 270, 330 ) configured to control operation of the coarse acquisition circuit and the fine acquisition circuit, and to provide a final acquisition phase as a current phase based on the one or more fine acquisition phases.
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