| 摘要 |
An interface circuit 200, suitable for inter-chip or intra-chip communication, contains edge detection circuitry 206, providing a short pulse at a rising and falling edge of a data signal, and driver circuitry 208 comprising a plurality of drivers, e.g. tri-state drivers, coupled in parallel. Driver circuitry provides a weighted sum signal and the drivers may be used to selectively adjust the amount of driver current provided onto a connection. Edge rate or voltage swing of the weighted sum signal can be determined by the number of drivers that are turned on. Component 214 receives an inverted data signal and modulates swing and edge rate of a leading edge signal; component 212 modulates the trailing edge. The weighted sum signal may be a sum of return-to-zero (RZ) and non-return-to-zero (NRZ) components of the data signal and can be recovered using an inverter. Interface circuit 200 may be used when stacking dies (102, 104, fig. 1). |
