发明名称 PROCESSOR
摘要 <p><P>PROBLEM TO BE SOLVED: To improve processing efficiency by shortening a wait time in performing read access to an external device as regards a processor equipped with a DSP core including a CPU or a DSP, and connected via a bus controller to an external bus, and configured to perform the read access to the external device connected to the external bus. <P>SOLUTION: A read buffer for performing read access to the external device is installed between a bus controller and a DSP core connected to the external bus in the processor, and the read buffer is provided with the register of a read address and read data and a flag, and the flag is set according to the read access to the external bus, and when the read is completed, the flag is reset, and the read buffer executes the read access according to the read address to the external bus when receiving the write access of an address from the DSP core, and sets the flag, and when receiving the read data, the read buffer resets the flag, and shows read completion. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008129672(A) 申请公布日期 2008.06.05
申请号 JP20060311076 申请日期 2006.11.17
申请人 FUJITSU LTD 发明人 UNO HIROAKI;KATO HIDEO;KOBAYASHI SHINICHIRO;NAKAYAMA YOSHIHISA;TERADA MASAYO
分类号 G06F15/78;G06F13/36 主分类号 G06F15/78
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