发明名称 WAFER LEVEL DEVICE PACKAGE WITH SEALING LINE HAVING ELECTROCONDUCTIVE PATTERN AND METHOD OF PACKAGING THE SAME
摘要 A wafer level device package with a sealing line having a conductive pattern and a packaging method thereof are provided to read an electrical signal from a device on a device region or apply power to the device by using the conductive pattern and a lead frame without using a separate electrode pad. A wafer level device package includes a device substrate(10'), a sealing line(20), and a cap substrate(40'). A device region(30) is formed on the device substrate. A device is mounted on the device region. The sealing line encloses the device region and includes plural non-conductive patterns and plural conductive patterns(22). The cap substrate includes plural vias(50) which are connected to the respective conductive patterns. The cap substrate is bonded with the sealing line. Plural lead frames(31), which are connected to the conductive patterns of the sealing line, are formed on an upper surface of the device substrate.
申请公布号 KR100826393(B1) 申请公布日期 2008.05.02
申请号 KR20070049834 申请日期 2007.05.22
申请人 SAMSUNG ELECTRO-MECHANICS CO., LTD. 发明人 HONG, JU PYO;CHOI, SEOG MOON;KIM, TAE HOON;HA, JOB;PARK, SEUNG WOOK
分类号 H01L23/28;H01L23/48 主分类号 H01L23/28
代理机构 代理人
主权项
地址