| 摘要 |
A method of fabricating an integrated circuit including strained silicon bearing regions. The method forms a blanket layer of material having an initial thickness overlying a source region, a drain region, and a gate structure of an MOS device to cover an upper surface of the gate structure, including the hard mask layer, to form a substantially planarized surface region from the blanket layer. The method removes a portion of the initial thickness of the blanket layer to remove the hard mask and expose a portion of the gate structure. In a preferred embodiment, the portion of the gate structure is substantially polysilicon material. The method introduces dopant impurities into the portion of the gate structure using at least an implantation process to dope the gate structure, while maintaining the source region and the drain region free from the dopant impurities.
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