发明名称 |
APPARATUS AND PROCESS FOR PATTERN DISTORTION DETECTION |
摘要 |
<p><P>PROBLEM TO BE SOLVED: To verify how finished patterns differ among a plurality of different process conditions and a plurality of different methods of forming verification layout patterns in a semiconductor manufacturing process. <P>SOLUTION: Differences among predicted pattern data are detected by predicting a plurality of finish patterns in accordance with a plurality of different pattern forming process conditions and/or a plurality of verification layout pattern data and by performing figure operation on the predicted plurality of finished pattern data. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
申请公布号 |
JP2008003633(A) |
申请公布日期 |
2008.01.10 |
申请号 |
JP20070233652 |
申请日期 |
2007.09.10 |
申请人 |
RENESAS TECHNOLOGY CORP |
发明人 |
TAOKA HIRONOBU;MORIIZUMI KOICHI |
分类号 |
G01B11/24;G03F1/68;G03F1/70;G03F1/84 |
主分类号 |
G01B11/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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