发明名称 LOGIC VERIFICATION METHOD, LOGIC VERIFICATION APPARATUS AND RECORDING MEDIUM
摘要 There is provided a logic verification method for performing logic verification of an integrated circuit by using device data defining functions of the integrated circuit. The logic verification method includes reading device data made up by a plurality of pieces of logic module data each including (i) first circuit data defining a predetermined function by using a hardware description language and (ii) second circuit data defining the same predetermined function by using a logic circuit including a gate circuit, wherein the second circuit data includes timing information for an operation performed over time, selecting one of the first circuit data and second circuit data for each of the plurality of pieces of logic module data making up the device data, and executing logic verification based on device data made up by selected pieces of circuit data.
申请公布号 US2007266361(A1) 申请公布日期 2007.11.15
申请号 US20070681056 申请日期 2007.03.01
申请人 ADVANTEST CORPORATION 发明人 YAMAMOTO KAZUHIRO
分类号 G06F17/50 主分类号 G06F17/50
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