发明名称 |
Output buffer receiving first and second input signals and outputting an output signal, and corresponding electronic circuit |
摘要 |
An output buffer is provided, to which first and second input signals are applied and that delivers an output signal. The output buffer includes a second offset switching stage installed in cascade downstream from a first switching stage. The second offset switching stage generates control points shifted in time with respect to memory points.
|
申请公布号 |
US2007250554(A1) |
申请公布日期 |
2007.10.25 |
申请号 |
US20070786424 |
申请日期 |
2007.04.11 |
申请人 |
ATMEL NANTES SA |
发明人 |
BENDRAOUI ABDELLATIF;CHATAL JOEL;GIBET STANISLAS |
分类号 |
G06F15/00 |
主分类号 |
G06F15/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|