| 摘要 |
PROBLEM TO BE SOLVED: To provide a hierarchical design method and device solving such the problem in hierarchical design that the total optimality of a result is lost due to problem division without deteriorating the advantage of the hierarchical design that a designing time can be shortened with less memory. SOLUTION: After arranging a gate level of a chip or wiring, one or a plurality of arbitrary layout areas on the chip are cut out and each of the cut-out areas is blocked, each of the cut-out blocks is redesigned, and design of the blocked area is replaced with a result of the redesigning to change a layout design of the chip. COPYRIGHT: (C)2008,JPO&INPIT
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