| 摘要 |
In one embodiment, a memory circuit comprises one or more first memory cells, each of the one or more first memory cells configured to store at least one bit; one or more second memory cells, each of the one or more second memory cells configured to store at least one bit; and one or more read port circuits physically located between the first memory cells and the second memory cells. Each of the read port circuits is coupled to receive the at least one bit from each of the first memory cells and each of the second memory cells, and each of the read port circuits is configured to output the at least one bit from a selected memory cell of the first memory cells and the second memory cells responsive to a plurality of wordline signals coupled to the read port circuit.
|
