发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To evade the number of external terminals of the semiconductor circuit from increasing when performing the control of test switches, supplying impressing signals for measurement, and outputting measurement results, at the external test of the semiconductor integration circuit provided with built in a plurality of analogue circuit blocks. SOLUTION: By a test mode designation signal (Norm/Test Mode), a semiconductor integration circuit (IC_Chip) is set to the test mode. To a plurality of analogue circuit blocks (Anlg_Cir1... Anlg_CirN), a plurality of switching circuits for testing (Tcnt_Sw1... Tcnt_SwN) for switching the signal paths from normal signal path in the test mode to that in the normal operation mode are connected. The test control interface circuit (Tcnt_Int) which is serially transmitted from outside with the control signal DI of a plurality of bits activates a plurality of switching circuits sequentially. In a plurality of analogue circuit blocks, the supply of the impressed signal for external measurement Tfd and control of the output of the measurement results Tdet are performed in order. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007187489(A) 申请公布日期 2007.07.26
申请号 JP20060004303 申请日期 2006.01.12
申请人 RENESAS TECHNOLOGY CORP 发明人 SAITO KAZUTAKA
分类号 G01R31/28;G01R31/316;G01R31/3185;H01L21/822;H01L27/04 主分类号 G01R31/28
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