发明名称 METHOD OF GENERATING TEST PATTERNS TO EFFICIENTLY SCREEN INLINE RESISTANCE DELAY DEFECTS IN COMPLEX ASICS
摘要 A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults ("TDF")) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.
申请公布号 US2007162804(A1) 申请公布日期 2007.07.12
申请号 US20070682914 申请日期 2007.03.07
申请人 LSI LOGIC CORPORATION 发明人 BENWARE ROBERT B.
分类号 G01R31/28;G06F11/00 主分类号 G01R31/28
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