| 摘要 |
PROBLEM TO BE SOLVED: To provide an integrated circuit which copes with variable cache size even after design of a cache controller is hardened. SOLUTION: An integrated circuit is provided with a cache memory and a cache controller coupled to the cache memory via a cache memory interface. The cache controller supports different cache memory sizes. The cache memory includes masking logic responsive to cache memory size signals to form masked address values for use in accessing the cache memory. The cache controller can be part of a processor core which maybe hardened in its design and yet able to cope with the variable cache memory sizes since the masking logic is provided within the cache memory outside of the hardened periphery of the processor core. COPYRIGHT: (C)2007,JPO&INPIT
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