发明名称 Method and system for optimizing latency of dynamic memory sizing
摘要 Some embodiments of the invention include a system and method for optimizing the latency of dynamic memory sizing. In some embodiments, the operating requirements can reflect amount of memory required to perform commensurate operations. Memory power management logic is used to coordinate memory requirements with operating requirements. The latency of changes to the memory based on operating requirements is optimized by the method and system. Other embodiments are described.
申请公布号 US2007156992(A1) 申请公布日期 2007.07.05
申请号 US20050323259 申请日期 2005.12.30
申请人 INTEL CORPORATION 发明人 JAHAGIRDAR SANJEEV
分类号 G06F13/00;G06F13/28 主分类号 G06F13/00
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