| 摘要 |
ESD protection circuitry for a signal power supply pad ( 801 ) comprising a discharge circuit ( 802 ) operable to discharge the ESD pulse to ground, and a precharge reduction circuit ( 810 ) in parallel with the discharge circuit. This precharge reduction circuit is operable to cancel any precharge voltage to ground before an ESD event, and also to discharge any trailing pulse to ground after an ESD event. The reduction circuit comprises a discharge resistor ( 811 ), preferably about 10 kOmega, connected to the discharge circuit, and a control MOS transistor ( 812 ) in series with the discharge resistor. The transistor source ( 812 a) is connected to the resistor, the drain ( 812 b) to ground, and the gate ( 812 c) to core power ( 813 ) so that the transistor is shut off during IC operation and conducting when pre-charge or post-charge is present at an ESD pulse.
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