| 摘要 |
A test-mode circuit allows the same pad of a semiconductor device to be used as a test pad during test operations and as an I/O pad during normal operations. The test-mode circuit is coupled between the pad and a reference signal (Vbg) of the device, and in response to a control signal (CTRL 1 ) either couples the pad and the reference signal (Vbg) together or isolates the pad and the reference signal (Vbg) from each other. The test-mode circuit includes at least one NMOS transistor (MN 1 ) and a PMOS transistor (MP 1 ) connected in series between the pad and the reference signal (Vbg). During normal operation, the NMOS transistor (MN 1 ) isolates the reference signal (Vbg) from the pad, and the PMOS transistor (MP 1 ) compensates for voltage undershoot conditions at the pad.
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