| 摘要 |
A method for modifying a design of an original processor that is capable of running binary code with a given cycle-by-cycle execution pattern and includes an original pipeline having multiple phases. Each phase of the original pipeline is divided into at least two sub-phases, thereby providing a modified pipeline. Register sets and logic are coupled to the modified pipeline so as to create a multithreaded processor that is operative as a plurality of virtual processors, which have respective virtual pipelines supporting different, respective threads and which are able to run the same binary code as the original processor in each of the threads with the same cycle-by-cycle execution pattern as the original processor.
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